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By Jameel Menashi

Aqueous solutions of Na2Cr04 can be reduced with CO to produce hydrous Cr203 and NaHCO3/Na2CO3. CH3OH, HCOO and HCHO in the presence of CO2 also reduce Cr 6+ and yield similar products. It is shown that the rate of Cr6+ reduction can be represented by the expression -d[Cr6+]/dt=k[Cr6+)1/2[R] where [R] is the aqueous phase concentration of CH3OH, HCOO- or CO. With these three reductants, the activation energies for the reduction processes are comparable and are of the order of 100 kJ/mole. Rapid reduction rates are attained at temperatures in excess of 220°C and, with these three reductants, a green acid-insoluble readily filterable hydrous Cr203 is formed. With HCHO significant reduction of Cr6+ occurs at about 80-100°C and an acid-soluble violet modification of hydrous Cr2O3 is formed. The reduction process is reasonably selective: solutions of Na2CrO4 contaminated with Mo6+ and W6+ can be reduced to yield a Cr2O3 product with significantly reduced contaminant levels. These findings are utilized as a basis for a process for recovering chromium from secondary source materials.

Jan 1, 1984

By Earl G. Alexander, W. R. Runyan

The nature of silicon growths which form on amorphous silicon dioxide during epitaxial deposition in unmasked areas was investigated. Octahedral silicon crystals nucleate and grow on the oxide at pinholes, adjacent to foreign matter, and probably at oxygen-deficient sites. Generation of these oxygen-deficient sites on the oxide surface is shown to be thermody-namically favorable under usual deposition conditions. The conditions which affect saturation (SiCl4 concentration, flow rate, temperature) determine the number of sites on which silicon will nucleate and grow. Reaction product HCl is likely responsible for suppressing silicon growths on the oxide near exposed areas of silicon. Evidence is given that the oxide-silicon interaction occurs in hydrogen only and involves water as a transport agent. SINCE shortly after the first epitaxial layers of silicon and germanium were grown over large areas, efforts have been underway to grow selectively on specified portions of the surface. Such selective growth should be particularly applicable to monolithic integrated circuits. Usually the approach has been to use a mask to delineate the desired area,'-7 but the VLS methoda can also be used, and direct programmed atomic beam deposition has been suggested.9 The masking techniques may embody two forms: in one the mask is a material which can later be removed along with any growths attached to it; in the other, attempts are made to prevent growth on the mask, so that over a whole slice the only deposition that will occur is in the unmasked regions. The present work is concerned with only the latter case, and specifically with silicon. Joyce and Baldrey1 suggested the use of thermally grown silicon dioxide as a mask material and showed that for the proper choice of operating conditions (total flow, SiCl4 concentration, total deposition time, and temperature) spurious growth could be minimized and that if the deposition times were not too large, and the criteria not too stringent, a usable process occurred. Later Schnable et al 4 observed that after extended deposition times, during which most of the silicon dioxide became covered with growth, there was always a band of oxide around the exposed silicon area that was quite free of spurious silicon crystallites. This latter observation is particularly intriguing since it extends the hope that with proper precautions masking can be much more versatile than it presently is. EXPERIMENTAL PROCEDURE Silicon substrates oriented to within 1.5 deg of a (111) plane were prepared by etch polishing lapped

Jan 1, 1967

By E. R. Dean

A wire-feed mechanism has been employed to fabricute metal alloy film resistors to various sheet resistivities on oxidized silicon substrates. The effect of several thousand hours storage in air at elevated temperatures on the resistance and temperature coefficient of resistance is presented. Unprotected films of- sheet resistivity between 100 and 500 ohms per sq fabricated at 300°C substrate tenzperatures were unstable when stored at 150°Cfor extended periods. The higher sheet resistivity films exhibited the greatest instability; however, even the 100 ohms per sq films drijted excessively for device application. When stored at still higher temperatures, the normalized resistance increases to maximum, then decreases until a minimum value is obtained, then finally increases in resistance until open. The use of a protective overcoating of SiO has had considerable benejicial effects on the film stability, so that 250 ohms per sq films deposited on 300°C substrates are now stable after 1000 hr storage at 250°C and possess a temperature coefficient of resistance less than 200 ppm per C. The use of a low substrate temperature during depositon (100°C) enables the preparation oj resistors with very low tenperature coefficients of resistance (10 to 20 ppnl per 'C). However, these films are less stable than their higher substrate temperatuve counterparts. During extended storage, the resistance of the protected films always decreases with lower substrate films exhibiting larger normalized resistance decreases. This resistance decrease is accompanied by a linearly related increase in the temperature coefficient of resistance. The electrical behavior of these films may be explained by postulating That the structure of the films is in the transition region between thick continuous films and ultrathin island structure films so that the conductivity is the restlt of both electron scattering and tunneling-activated charge carrier creation between neighboring grains. The annealing behavior when thermally aged is the result of defect anneal, grain growth, and selective oxidation. TheRE is a considerable interest in thin metallic films for use as resistor elements in microelectronic circuits.1,2 These resistor films must be stable when exposed to elevated-temperature storage or operating ambient, possess low temperature coefficients of resistance (hereafter referred to as T.C.R.), and be of a high enough sheet resistivity to be useful. The resistivity and T.C.R. of a thin metallic film are determined by the structure and thickness of the film. Hence the stability of the film when exposed to stress would depend on the stability of the structure. The resistivity of a thin film is the result of the electrons' interaction with the lattice vibrations (electron-phonon scattering), scattering of electrons due to impurities, defects, and grain boundaries and specula reflection from the film surfaces.3' All of these effects serve to reduce the electron mean free path and result in a resistivity higher than the ideal bulk. In ultrathin films possessing essentially an island structure consisting of a planar array of aggregates separated by a few to a few tens of angstroms, conduction is dominated by a combination of tunneling and activated charge carrier reation. Thin films would be characterized by relatively low resistivity, positive T.C.R., and reasonable structure stability whereas ultrathin films possess unstable structures, negative T.C.R., and exhibit high resistivity. Feldman6 has investigated films intermediate between the two regions and postulates that the resistivity of a film in the transition region is composed of two linearly additive parts: that due to the resistance of the grains and that due to the gaps. The grain resistivity would represent the scattering of the conduction electrons by defects, surfaces, and phonon interaction while the gap term represents the tunneling contribution. For gold and platinum films, he found as the film structure becomes progressively less continuous, corresponding to thinner films, the absolute value of the T.C.R. becomes progressively smaller until negative values are observed with respective zero T.C.R.'s at about 35 and 150 ohm per sq, respectively. Recently the author7 investigated the behavior of a multicomponent alloy of nickel, chromium, and iron and found the T.C.R.'s of these films decrease with decreasing substrate temperature during deposition. The lower T.C.A. associated with lower substrate temperatures was attributed to an increased contribution to the total resistivity from the negatively temperature-dependent gap tunneling since it is well-known that thin films deposited on low-temperature substrates consist of a higher density of smaller grains than the same sheet resistivity films deposited on higher-temperature substrates. Under conditions of thermal anneal, the author found that, when various sheet resistivity films fabricated at 300°C substrate temperature are exposed to extended storage in air at 300°C, the thinner films increase in resistance until open, while the thicker films

Jan 1, 1967

By H. Bartholomew, L. Bernstein

Experirmental bonds of Ag-In SLID to gold, copper, nickel, Kovar, Dumet, nickel-plated molybdenum, ALL-Pt vrzetallizing on ceramic, and nickel-plated Mo-Ti metallizing on Al2O3 ceramic have been made and exalnined. Metallographic taper sections were made of all bonds for Phase identification. In addition, failuve temperatltres were determined for bonds heated undev shear load. Sowe bonds were subjected to electvon-probe microanalysis. The ternary SLID system Ag-In-Sn was similarly evaluated. Plwtonticrogaphs and electron-probe data are discussed and related to over-all phase diagrams , diffusion effects, and wetting properties of the liquid. The rates of diffusion andor compound formation of gold, silver, and copper in indium and In-Sn liquids are found to descend in that order, as measured by the relatzve thickness of phase layers in the interfaces of bonds made at 200to 400°C. It is concluded that the SLID process enables one to produce bonds which are stable at high temperatures, after having been fabricated at low temperatures, and meet most requirements for application in interconnection, silicon bonding, or hermetic sealing of electronic devices. In a previous publication by one of the authors, the theory and principle of SLID bonding in simple binary systems was discussed. SLID bonding can be defined as a joining process using a preform with a laminated structure: a low-melting material clad on a high-melting core. During the bonding cycle a metallurgical transformation occurs such that the resultant structure can withstand, without reliquefying, temperatures higher than those at which the bond was made. The phases present in the joint interface region are high-melting compounds or, if equilibrium is reached, solid solution. Properties will depend on the phases present, ultimately approaching those of the solid substrate core of the SLID preform. The high-temperature strength of bonds made in these systems was correlated to phase identification in the interfacial bond regions from metallographic cross sections and electron-probe X-ray microanalysis data. When complex electronic components are assembled, multiphase systems result at the interfaces of bond regions. In these ternary and higher-order systems very little diffusion and phase-diagram data is available with which to predict the nature of the interfacia1 region that will result from conventional fabrication processes and subsequent field use of the component. Clarke and Rhines did early work in the field using the Al-Mg-Zn system as a vehicle. Guy and co-workers studied a portion of the Cu-Zn-Ni system and some mathematical4 and general5 aspects of multiphase diffusion. irkald' and coworkerse recently studied diffusion in the Cu-Zn-Sn system. No diffusion studies have been made on ternary systems directly applicable to this investigation but some phase diagrams are available: g-u-n, u-i-n, and CU-i-n. I) DESCRIPTION AND EXPERIMENTAL PROCEDURE The elements Au, Ag, Cu, Ni, In, and Sn are found in alloy systems commonly used in fabricating and assembling electronic components. Reference to the appropriate phase diagrams9 and the previous publication will indicate that the binary systems of any of the two low-melting elements, indium and tin, with any one of the other four higher-melting elements are capable of producing SLID bonds. It is not unreasonable to assume that any ternary or higher-order alloy system containing at least one of the elements gold, silver, copper, or nickel and one or both of the elements indium and tin could be used to produce bonds which are stable at high temperatures, after having been fabricated at low temperatures. Indeed, the liquidus contours and isothermal sections of those phase diagrams available7 do so indicate. The parameters affecting the bond and the equipment used in evaluating the bond were described in an earlier paper.' The current investigation used the

Jan 1, 1967

By K. E. Manchester, C. B. Sibley

The feasibility of doping silicon to produce device structres by directly implanting impurity atoms has been demonstrated. Both phosphors and boron ions have been successfully implanted in silicon to produce electrical junctions. Junctions as deep as 1.2 p have been produced by phosphorus ions having energies the order of 80 kev. An electromagnetic separator has been used to controllably produce uniform, large-area implantations for evaluation experimentation. Correlations between junclion depths and ion energies huve been obtained. Orientation effects have been observed and it has been found that the (110) direction is the easy direction for implanting. Monitoring of thermal treatments oj implanted substrates by sheet-resistance measurement indicates a very mild thermal anneal removes most of the damage done during the implantation. These indications are further substantiated by reverse-current measurements of j,inctions Produced by implantation. Electrical characteristics of implanted junctions are compared with those of diffused junctions. We have been interi n the interaction of energetic ions in the III-V groups, in particular boron and phosphorus, with single-crystal silicon to produce type conversion for possible device use. A number of investigators, a few of whom are avies, Kornelson,3 and so forth, have reported on penetration of energetic ions into both amorphous and crystalline solids. While most work has been done with ions of the rare gas and alkali metal groups, some work has been reported by ing, erber,' and others6 in which ions of the 111-V groups have been implanted in single-crystal silicon. A large amount of this work has been done with ion energies in the 100-kev to 1.5-Mev range. An excellent review article has been written by caldin. We have concentrated on ion energies which are in the 10 to 80 kev range, with which over 1500 implanted junctions such as the one shown in Fig. 1 have been produced in silicon substrates with both phosphorus and boron ions. Fig. 1 is a 3-deg angle lap in which the n type area produced by 66 kev P is delineated and the junction is 9500A below the surface. EXPERIMENTAL Implantations reported in this paper were made with the ion source adjusted to produce ion currents in the range of 1 to 2 pa with accelerating voltages varied from 10 to 40 kv. When using doubly charged ions this produced 10 to 80 kev ions. This allowed substrate temperatures to remain below 100°C. Sam- ple movement resulted in beam impingement angle variation of 7 deg from the normal to the substrate surface. Substrate resistivities have been varied through the range of 0.001 to 500 ohm-cm and specimens oriented in three directions, (110), (Ill), and (loo), within 12 deg. RESULTS For the purpose of this paper, discussion of results will be limited to phosphorus implantations with mention of results for boron-implanted silicon. Similar results have been obtained for boron and will be reported at a later date. In Figs. 2, 3, and 4 depth penetration is shown

Jan 1, 1967

By L. A. Weitzenkamp, N. M. Bashara

A study of the electrical conductivity of gold films less than 200 in thickness indicates a negative temperature coefficient of resistance and a thermal actiuatlon energy of less than 0.25 ev. The films consist of discrete metal islands of linear dimensions from a few angstroms to 1000A. Films were able to withstand applied fields up to 60,000 v per cm before breakdown occurred. A model for the conduction mechanism is proposed which involtes a Potential barrier due to work junction, irriage forces , and an electrostatic potential arising from separating an electron from a neutral island leaving behind a positively charged metal island. Activation energies of less than 0.25 ev ave consistent with this model, which includes a tunneling andor Thermal mechanism for conduction between the separate metal islands. An apparent satuvation effect in conductivity at high fields is observed experimentally. The saturation effect may be explained by the influence of the electrostatic contribution to the potential barriers for the transition through several islands adjacent to the original island which was activated to give up an electron. The proposed model gives Poor quantitative agyeement for the intermal electrical field between islands. ThIS paper will relate the structure of discontinuous metal films to the electrical properties and will emphasize the following topics: 1) the relation of the conduction mechanism to particle size and a comparison of particle size from electrical measurements with electron-microscope studies; 2) the saturation of the conductivity at high electric fields; and finally, 3) a comparison between the external field applied and the apparent field between particles. che- latter comparison points to a need for a modification in the model for the conduction mechanism first proposed by orter' and expanded by Neugebauer and webb2 which will be dealt with in the discussion. The paper is based on results on gold films on glass microscope slides. The clms were vacuum-evaporated and were about lOOA thick, thickness being measured by interferometry. It has been observed that metal films of this thickness do not exhibit bulk metallic conduction. Films thinner than some critical thiclmess, depending upon substrate temperature and other factors, have conductivities which increase with increasing temperature with thermal activation energies of less than 0.25 ev. Electron-microscope studies3 have shown that these films consist of discrete metal islands having linear dimnsions from a few angstroms to approximately 1000A. When the metal is being vacuum-deposited on the substrate, islands on the order of a few angstroms appear first. As the deposition continues the islands may tend to agglomerate into larger particles and may eventually grow together into a continuous film,3''' In our tests the conductivity of the gold films was found to be about ten orders of magnitude less than the bulk conductivity of gold. When oxygen was introduced into the test chamber the conductivity decreased by a factor of about one-third. This can be related to an increase in work function for gold caused by adsorption of oxygen, as reported by Oullet and Rideal.s Exposure to an atmosphere of water vapor caused an increase in conductivity by a factor of 2 or 3 when a low field was applied. When the films were exposed to water vapor under a high field the conductivity increased by as much as two orders of magnitude. The activation energies measured were much less than the work function for gold, 0.25 ev or less, with the smaller activation energies observed for thicker films. It will be shown that the activation energy is a function of particle size and spacing. In general the model for the potential between metal islands would include the effective work function, the image force, the applied field, and an electrostatic term. The electrostatic contribution arises from the potential required to separate an electron from a conducting sphere. According to Neugebauer and webb2 the maximum potential due to the field and the electrostatic term only is

Jan 1, 1967

Jan 1, 1967

Jan 1, 1968

By M. Khorouzan, L. Thomas

Designers of semiconductor devices have been strivi,ng to resolve problems associated with Au-A1 alloys in bonded in.tercomzeclions. One approach now being- used is that of waintaining a physical seyav-atioz between the two metals in bond areas. This is accolrzplished by alunzincnz-plating a bonding area on the tips oJ the kovar leads and using alcminurn wires to join the senzicondictor device to the leads. The portion of the kovar lead which is on the externul side of the sealed package is gold-plated to provide an oxide-free surface for soldering or welding. A discoloration condition originally thought to be sinilar to purple plague, occuving in the yluled uluninur bonding area after package sealing, has been investigated to determine its efiects ipm bond integrity. Electron-micro-probe analysis determined that no1 only gold, but lead, zinc, and silicon were also present in the discolored area. A series of samples conlaining' conkrolled umonts of these inzpitrities weve prepared and subjected to a sil.zuluted sealing process. The investigations swcued that, of the contawiinants, only zinc toas detrinenlul to Lhe bond integily. The discoloration condition itself was found not to be detrimental to the bond integrity. DESIGNERS of semiconductor devices have been striving to resolve problems associated with Au-A1 alloys in bonded interconnections. One approach now being used is that of maintaining a physical separation between the two metals in bond areas. This is accomplished by aluminum plating a bonding area on the tips of the kovar leads and using aluminum wires to join the semiconductor device to the kovar leads. The portion of the kovar lead which is on the external side of the sealed package is gold-plated to provide an oxide-free surface for soldering or welding. Contamination as evidenced by discoloration of the aluminum-plated area was observed in a number of integrated circuits undergoing examination for defect characteristics which cause electrical failures.' This paper contains the results of an investigation to determine the nature of this discoloration, its cause, and its effect upon the integrity of the interconnection bond. I) THE NATURE AND EXTENT OF ALUMINUM-BOND CONTAMINATION The initial hypothesis in the investigation was that the discoloration was caused by reaction of the aluminum film with some unknown contaminants during the sealing of the hermetically sealed integrated-circuit flat package. The package is a rectangular ceramic container sealed with glass which surrounds the kovar leads as well as joining the top to the bottom. The seal is made hermetic by heating and cooling the package to devitrify the glass. In the case of the packages under investigation, the hermetic sealing had been accomplished with dry air as internal atmosphere. The apparent effect of contaminations as observed by microscopic examination was the formation of surface oxides having variations in color encompassing the whole spectrum of visible light. The contamination appeared to be related to one of the more notorious examples of these colorations, the so called purple plague.' In addition to purple plague, Fig. 1 shows the tarnish in the luster of the aluminized surface in the bond area which had been observed in many of the integrated circuits. To identify the contaminant in the bond area electron-probe microanalysis techniques were used.3 Fig. 2 shows the result of this analysis. The contaminants identified were gold, aluminum, zinc, lead, silicon, and cobalt. Fig. 2(a) is a back-scatter display of the area under study. The back-scattered electrons provide a general indication of the distribution of elements in the specimen surface. Elements with higher atomic number scatter more electrons back from the surface and are seen as light areas in the picture. The sample current, Fig. 2(b), is the amount of current conducted by the specimen as a result of electron-beam striking it and is an indication of element distribution. The Sample current is the reverse of back-scatter and complements it. Other pictures in Fig. 2 are produced by characteristic X-rays generated by the elements, allowing the isolation of the element of interest. The isolated element appears white and all other elements are dark. In this manner a comparative study provides a correlation between different surface areas and the elements which are in these areas. The area covered by the gold film, Fig. 2(c), shows that the boundary between the gold film and the kovar is not sharp as expected and that some sort of diffusion has taken place. Fig. 2(c) shows that some gold particles have been carried to the bond area and are in the proximity of the bonded wire in spite of the presence of a physical barrier in the form of the un-

Jan 1, 1967

By Hollis L. Caswell

The present status of integrated circuits utilizing. superconductive switching. elements is reviewed with special attention given to fabrication techniques, methods for interconnecting completed circuits, and refrigeration requirements. Cryoelectronics has been largely an "inte- grated-circuit" technology since its conception because the switching speed of superconductive devices is attractive only when these devices are fabricated with thin-film techniques. It is true that cryotron circuits can be constructed from wires of appropriate materials (as indeed was done by Dudley Buck 1 in his early investigations) but these circuits will switch in times characteristic of milliseconds whereas similar circuits fabricated by thin-film methods have potential switching times of nanoseconds. Furthermore, cryo-electronic devices such as the cryotron lend themselves readily to fabrication by thin-film techniques since these components may be made from polycrys-talline thin films and are relatively insensitive to the presence of impurities (as measured by semiconductor standards). Therefore, during the past decade considerable effort has been devoted to developing techniques for batch fabricating circuit arrays containing superconductive switching elements. Technology had developed to the point several years ago that fabrication of cryoelectronic arrays containing up to one hundred devices was rather straightforward. However, larger arrays containing between lo4 and 106 components which are required for commercial development of cryoelectronics still pose very severe yield problems. Thus in a sense cryoelectronics found itself in 1962 at the point semiconductor technology finds itself today; namely, individual devices and small groups of integrated devices could be fabricated with acceptable yield and the outlook for building larger integrated-circuit arrays was bright. Unfortunately, problems associated largely with yield have made fabrication of these larger arrays difficult. Unlike semiconductor technology, cryoelectronics had to solve the problems of large-scale integration before it could become economically attractive. This has proven to be a sizable burden to bear. Since several reviews exist on superconductivity,2 superconductive devices,3 and cryoelectronic technology, no attempt will be made in this paper to summarize these areas. Instead a few specific topics will be dealt with in more detail. First, a brief description is given of selected superconducting switching and storage devices with special attention to several metallurgical techniques which improve the performance of these devices. Second, techniques used to fabricate cryoelectronic devices are described with emphasis on problems affecting yield. Third, techniques for interconnecting a number of cryoelectronic planes are described. And last, refrigeration of cryoelectronic components is discussed briefly since the low operating temperature of superconductive devices is an important consideration in this technology. SUPERCONDUCTING STORAGE AND SWITCHING DEVICES The basic superconductive switching device is the thin-film cryotron. The geometry of this device is attractively simple, since it involves only the intersection of two lines that are electrically insulated from each other. The switching element (gate) and control element (control) of a crossed-film cryotron are arranged as illustrated in Fig. 1. The material for the gate is selected to permit the gate to be switched from the superconducting to the normal (resistive) state by the application of a control current. Tin, which has a critical temperature (T,) of 3.7°K, is commonly used for the gate and the cryotron is operated at a temperature just below T, (for example, 3.5°K). The control material (normally lead, with T, = 7.2°K) is chosen so that the control is never driven normal during circuit operation. To improve cryotron operation, a ground plane, also of lead, is placed under all of the circuitry to act as a diamagnetic shield and improve the current-density uniformity across the width of various thin-film elements. Normally, line widths vary from 0.005 to ^ 0.020 in. and film thicknesses from 300 to 10,000A, although new fabrication techniques make narrower lines feasible. In fabricating cryotrons it is important that the edges of the gate elements be geometrically sharp to avoid undesirable switching characteristics associated with a thinner edge region, Fig. 2. One technique which has been used extensively to form patterns consists of placing a physical mask containing the film pattern between the evaporation source and the substrate and depositing through the mask. Film strips formed in this manner possess a penumbra at the film edges due to shadowing of the evapor-ant under the mask. Several techniques have been proposed for minimizing effects due to this penumbra. One of the more promising metallurgical techniques

Jan 1, 1967

By R. M. Lumley, J. D. Wood

In this investigation, polyethylene terephthalate (Mylar) was coated with various thicknesses of a vapor-deposited silvel- precoat followed by a uapor-deposited zinc using several orders of- magnitude variation in deposition rate of both the silver and zinc. The grain size and resistivity of the zinc film was primarily a function of the silver precoat thickness (in the range of 0.001 to 10 average Agprecoat thickness) and a secondary function of the zinc film thick-ness. The silver and zinc deposition rates were found to have a minor effect on the characteristics of- the zinc film. Electron and X-ray dilffraction results slwwed that all zinc films exhibited a fiber texture mith the (0001) axes essentially perpendiculav to the platze of the film When coating nonmetallic substrates such as paper or plastics with zinc metal vapors, it is found that the zinc will not condense unless extremely high evaporation rates or very low substrate temperatures are used. In 1931, Fraser' reported a procedure whereby zinc could be made to condense on nonmetallic substrates by depositing a very thin precoat of silver. Utilizing Fraser's method, the ermans' developed a commercial process of making "metallized film" capacitors during World War 11. The metallizing process, which was introduced in the United States shortly after the conclusion of World War 11, became one of the first large-scale commercial applications of vapor-deposited metal films and remains one of the larger applications in the electronics industry. The process, as developed by the Germans, consisted of depositing a thin precoat of silver on lacquered, kraft paper followed by a conducting layer of zinc. The resulting silver-zinc film was used as the capacitor The term silver-zinc will be used throughout thiz paper to mean a metal film formed by an extremely thi layer of silver, 10A or less in average thickness, and a zinc film IOOA or more in thickness deposited on the silver film. ---. electrode with the lacquered paper being the dielectric. When polyethylene terephthalate was marketed by E. I. Du Pont Co. in the early 1950's under the trade name Mylar it was substituted for the kraft paper in many capacitor applications. Even though manufacture of metallized paper and metallized Mylar capacitors has been a large commercial process for many years, little information has been published about the deposition parameters. Correlating the work of others to the various effects to be expected of deposition parameters on silver-zinc films deposited on Mylar, it is expected that the

Jan 1, 1967

By William K. Antle

The successful application of ther mo compression lead bonding to semicondtctor or thin-film electronic devices depends on the establishment of the associated parameters. The quality of a thermocompression bond is primarily related to the process temperature and bonding force. A technique using the coelyicient of friction is presented that both reduces the time necessary for determining optimum parameter values and increases the accuracy of the results. Modern theories of the friction process are used to develop mathernatical expressions for shear and tensile bond strengths in terms of friction measurements. A further application of the pararneter-deterlnination technique concerns the measurement of surface contamination that may affect thermocompression bonding. In spite of the extensive use of thermocompression bonding, adequate methods for determining the bonding parameters have not been utilized. The quality of the weld depends on the temperature, force, and time used. There is a definite value or range of values for each parameter which assures an optimum weld. The process now generally used to obtain these values is to make several weld samples at each parametric setting, determine the mean pull strength, and relate the maximum consistent strength to optimum weld conditions. This could involve a very large number of test samples if a thorough search of each parameter were made. Experience and prior knowledge can reduce this number somewhat by limiting the investigation to a range known to contain the correct value, but the time and effort involved are still objectionable. The problems associated with thermocompression bonding of interconnecting leads to semiconductor or thin-film devices can be alleviated by the application of a new technique for establishing the process parameters. Obtaining the correct temperature, force, and duration to assure an optimum bond is accomplished by a simple measurement of the coefficient of friction. This approach increases the accuracy of parameter determination and greatly reduces the time necessary to complete the process. The approach made can be better understood by analyzing the principles of adhesion and friction on which thermocompression bonding depends. When two flat polished surfaces are placed together, the area of actual contact is much less than the apparent area determined by the over-all dimensions of the surface. This is because the microscopic surface is covered with projections which prevent uniform contact. Careful measurements of the electrical resistance across the contacting surfaces indicate the actual area may only be 1100,000 of the apparent area.' Because the actual contact area is small, extremely high pressure results from moderate force. This will produce deformation and plastic flow at contact points of the microscopic projections. The process will terminate in the creation of a large number of minute welds formed at extreme pressure and cold-worked to strong, hard bonds. Load removal will generally result in fracture of most of these microbonds because of the residual elastic stresses, unless the materials are soft. Friction between metals is due to the formation and

Jan 1, 1967

By Bernard G. Carbajal

The dielectric properties and thermal stability of glow-discharge polytnerized films of styrene, chloro-benzene, and other organics and photoresist filrns are presented. Variations in the glow-discharge polymerization procedure are related to thermal stability. Thermal treatwzents to improve the dielectric properties of both positive (A2 340) and negative (KMER) photoresists are given. THIS study of the dielectric properties of thin organic polymer films is part of a program to investigate the electronic applications of organic materials. Thin organic polymer films have been produced in an ac glow discharge,13 with a low-energy electron-beam process,4 and in an rf dicharge. A process has been developed during the course of this program for forming thin organic polymer films in a dc glow discharge. These glow-discharge polymerized (GDP) films exhibit some useful dielectric and insulative properties. Variations in the properties of the GDP films can be induced by changes in the source material (monomer) andor in the conditions of the glow discharge. Thin organic polymer films can also be produced from typical positive and negative photoresists. Some variations in the properties of the photoresist films can be induced by suitable post-application treatments such as thermal crosslinking. The properties of interest in this study are dielectric constant, dielectric strength, resistivity, and thermal stability. POLYMER FILM PREPARATION I) GDP Films. The GDP films were prepared in a dc glow discharge in an atmosphere of organic monomer vapor. The details of the glow-discharge procedure have been presented previously.6 Briefly, under the influence of a dc glow discharge organic vapors can be polymerized in the vapor phase and the resultant polymer (GDP film) deposits on and in the vicinity of the cathode. Substrates placed behind a screen cathode can be uniformly coated over all exposed areas. Pattern definition can be achieved using normal mask stencil techniques. Table I presents the pertinent parameters in the preparation of GDP styrene. Conditions of Forrrzation of GDP Styrene. The rate of deposition for GDP films was monitored using a current-time integrator. The thickness of the deposited film for a given set of experimental conditions was a function of the current-time integral. The fifth row in Table I is a compilation of the deposition rate of GDP styrene films. Other organic monomers behave in a similar fashion. With the exception of the highly halogenated saturated hydrocarbons, all organics subjected to the conditions of the glow discharge form GDP films. 11) Photoresist Films. Photoresists are normally recognized to exist in two forms, a low molecular weight, soluble polymer form (A) and a high molecular weight, crosslinked insoluble form (B). Typical negative photoresists are applied in the low molecular weight form A and converted to the high molecular weight form B by the action of light. (Positive photoresists are applied in form B and converted to form A by the action of light.) Eastman Kodak Metal Etch Resist (KMER) has been chosen as a typical negative photoresist. Polymer film samples were prepared in the same configuration used for GDP films. The KMER was applied in the usual fashion using a 120°C drying step (infrared-lamp heating) and a 180°C post-bake. Care must be taken to completely remove the solvent in the drying step and to properly develop and postbake to exposed photoresist. If the photoresist film is not properly dried and postbaked, severe blistering and peeling will occur during subsequent elevated-temperature exposure. Thickness can be controlled by varying the viscosity of the form A photoresist and the spin rate at application. AZ 340 was chosen as a typical positive photore-

Jan 1, 1967

By F. V. Shallcross

Physical properties of thin films of CdS and CdSe formed by vacuum deposition onto glass sibstrates have been studied as a function of deposition and processing conditions. The crystallinity and surface features of CdS films were examined using electron microscopy and electron and X-ray diffraction techniques. The films were poly crystalline; the preferred orientation and crystallite size increased with film thickness, substrate temperature, and deposition time. The CdS films consisted primarily of hexagonal-phase material, in contrast to similarly prepared CdSe films which have previously been observed to contain mixtures of cubic and hexagonal phases. As-deposited CdS films showed no major dependence of Hall mobility on crystallite size or degree of preferred orientation. Hall mobility and carrier concentration in CdS and CdSe .films were measured at various temperatures; both parameters increased with temperature and yielded activation energies which depended on fabrication conditions. Surface-desorption phenomena and overcoating of the semiconductor with SiO affected the observed electrical properties significantly. THIN films of cadmium sulfide1,2 and cadmium sele-nide3,4 have been employed by various workers as semiconductors in the insulated-gate thin-film field-effect transistor, known as the TFT. These devices are most commonly made by vacuum deposition of all materials onto an amorphous substrate such as glass. A knowledge of the microstructure and electrical properties of semiconductor layers used in the thin-film transistor is essential in order to form a realistic model for the device and to improve its performance, reproducibility, and reliability. This paper will describe studies of the physical properties of vacuum-deposited CdS and CdSe films prepared under various conditions. Structural characteristics examined in- cluded phases present, crystallite size, nature of preferred orientation of crystallites, surface roughness, and structural homogeneity throughout the film thickness. Electrical properties measured were Hall mobility and conductivity and their dependence on temperature and ambient. Thin-film properties are affected by many fabrication parameters including purity and physical form of evaporant, deposition rate, film thickness, design and temperature of the evaporation crucible, geometry of the deposition chamber, nature of the residual atmosphere, composition and temperature of the substrate, and details of postdeposition processing. PREPARATION OF FILMS In this work the semiconductor films were deposited in a conventional oil-diffusion-pumped system with pressures in the 10-8 torr range. The CdS evaporant was obtained from the Eagle-Picher Co. as a high-purity coarse-grained crystalline powder; the CdSe was a high-purity sintered powder supplied by the Harshaw Chemical Co. The evaporation crucible was a resistance-heated molybdenum-wire basket coated with aluminum oxide and filled with a quartz wool plug at the top. The source to substrate distance was usually 10 cm. This region was enclosed by a Pyrex inner cylinder. The substrate was heated with an overlying Pyrex plate coated with tin oxide. The substrate temperature was controlled using a thermocouple attached to the lower side of the heater. This thermocouple was calibrated against another thermocouple attached to a dummy substrate and by observation of melting points of various metal films deposited in the system. The substrates were polished borosilicate glass plates and conventional glass microscope slides. Substrate preparation included cleaning with an ultrasonically agitated detergent bath followed by isopropanol-vapor de-greasing. Film thickness was measured interferomet-rically during and after deposition. STRUCTURE OF CdS FILMS Structural studies were performed on CdS films using electron diffraction, electron microscopy, and

Jan 1, 1967

By T. G. R. Rawlins, L. E. Brosselard

Direct platinum carbon replicas have been used to study substrates prior to growth and after initial nu-cleation of the layer. Replicas have been directly stripped and correlations have been made with other replica techniques. Mechanically polished substrates are very flat with occasional areas of "dirt", which is apparently silicon. When such substrates are etched in hydrochloric acid gas, scratches and hexagonal defects (thought to be polishing compound) are revealed, together with areas of apparent redeposition. Chemically polished substrates are much less flat although much more homogeneous in appearance. Heat treat)nents have no effect. Nuclei deposited on these surfaces, using a normal silicon tetrachloride system, have been examined. Nuclei on mechanically polished subsrates occur in random areas only, whereas on chemically polished surfaces they are more uniformly distributed. THE interest in the study of thin films and now their rapidly expanding use in many fields has increased over a period of years. Much of this current interest, particularly in the field of single-crystal or epitaxial thin films, has derived its stimulus not only from possibilities for application but also from fundamental electron-microscope studies which have indicated the manner of growth of such layers from the initial nuclei.1-5 Previous work involving study of growth processes may be divided into three categories. First, vacuum deposition, primarily of metals, on a variety of substrates has been studied by electron microscopy and electron-diffraction techniques. These have shown the three-dimensional aspect of nucleation and the remarkable liquidlike behavior of the growing nuclei which coalesce to form a complete layer. More recently this work has been expanded in two ways: by growth inside the electron microscope this has obvious advantages for kinetic studies; and by growth in ultrahigh vacuum—much of this work has been done on semiconductors.8-11 It is of interest to note that metals, specifically gold deposited on rock salt, will form only polycrystalline layers in ultrahigh vacuum unless the substrate surface is contaminated.12 In general the mode of growth for vacuum-deposited semiconductor films is the same as that for metal films. The second method of growth that has been studied is that of electrodeposition.13,14 The little that has been published suggests that the mode of growth is similar to the vacuum case, except that irregularities may perturb the electric field and disturb the growth process. The third and last primary method of growing epitaxial layers is by use of chemical methods. These techniques have generated much interest and much has been published on them. Considerable electron-microscope work has been done on the defects in the layers; however comparatively little work has been undertaken on the initial nucleation and early stages of growth. Confining ourselves now exclusively to the case of silicon, Charig et a1.15 have considered the growth of silicon on silicon substrates by hydrogen reduction of trichlorosilane, and studied the films by means of replica and transmission techniques. Subsequently they have studied the same system for growth on quartz,16 and with the addition of pyrolysis of silane on quartz and alumina.17 Also Manasevit el al. have studied deposits using silane and silicon tetrachloride on sapphire.18-14 Finally, in this volume studies of deposition on beryllia and sapphire are reported. Although Revesz and Evans20 have examined complete layers, grown by means of the widely used silicon tetrachloride reaction, no detailed examination similar to that published by Charig and Joyce21 for the trichlorosilane system has been given. Therefore this investigation has examined substrate surfaces prior to growth and then nucleation on these surfaces for the silicon tetrachloride system. EXPERIMENTAL In this work the surfaces have been studied by means of standard replica techniques. Because of the very real problems associated with artifacts introduced,22 different replicas and different cleaning

Jan 1, 1967

By J. P. Pritchard, J. T. Pierce, O. G. Slay

This paper discusses the results of a technology-evaluation program to ascertain the feasibility of a piotornask-photoresist technology developed for fabrication of multiple-layer thin-film superconductive circuitry. The uehicle selected for this evaluation was a 120-bil associative data processor requiring a set of nine photomasks to define a similar number of patterned material layers of lead, tin, and polymer insulation. A total circuit area of 4 sq in. involved 2500 actitle and 12,000 passive crossings. Several short-free, electrically continuous specimens were satisfactorily completed under this program. Problems encountered in the preparation and use of the requi-ed set of Photomasks are discussed, as also are the problets of providing suitable external connections. A major retarding factor in the development of the superconducting thin-film cryotron technology for many years was the absence of batch fabrication means yielding necessary device density and count per substrate for practical applications. Early workers in the field desired only limited numbers of devices to permit careful study of discrete devices and representative circuitry integrating logic and memory capabilities. For these purposes mask stencils could be formed to selectively control the placement of materials, sequentially vapor-deposited in vacuum, to form the multilayer structure. In general a distinct pattern was required for each material layer; therefore, mechanical provisions were required to change not only the material source, but the patterning mask as well, before each deposition. All deposition steps were preferably performed in a single evacuation of the deposition chamber. Thus the means for storing, transporting, and registering masks and sources with respect to the substrate existed and were operated within the vacuum environment. In the authors' experience, the approach was and remains serviceable for preliminary device study, but was not extensible to an economical manufacturing method by virtue of the difficulties inherent in mask stencil preparation and use, and the capital investment implicit in the mechanization requirements. Since the commercial attraction of the cryotron technology stems principally from its potential for economical batch fabrication, the authors' program has placed major emphasis on fabrication methods. A highly useful method has evolved through adaptation

Jan 1, 1967

By William F. List, Marvin A. Schuster

Monolithic electrooptical mosaics of 2500 photo-transistor elements with internal row and surface column interconnections have been fabricated by epitaxial-planar diffsion techniques. Unique access to any elemed of the mosaic is provided through one of the fifty X and one of the fifty Y external leads. The sensor mosaic can be used for imaging applications and has a 1:1 aspect ratio, a resolution of 100 lines per in., a dynamic range in excess of lo3, a sensitivity of 0.5 per pw, element response within a 2:l range over 75 pct of the mosaic, and a minimum detectable signal of the order of 10-' w. Design considerations which ilnpose particclar fabrication yequirements are disctussed along with some of the problems peculiar to the epitaxial and planar-dijfision techniqes by which this device is fabricated. The solid-state silicon monolith has an imaging area of 0.5 by 0.5 in. and an element center -to- center spacing of 0.010 in. J monolithic solid-state electrooptical device has been developed as the photon-sensing mosaic for use in an image-converter system.' This system is the solid-state equivalent of the vidicon and can image radiation in the visible and near-infrared regions of the spectrum. The electrooptical image converter has the desirable size, weight, reliability, and low-power characteristics inherent in solid-state devices. It is read out by direct-wire means rather than by beam-scan techniques. The packaged unit is shown in Fig. 1. A selection of material for the sensor was based on considerations of both reliable fabrication techniques and material spectral response. Silicon was selected both for its response from the lower end of :he visible to the long-wavelength cut-off above 11,000A and for its well-developed epitaxial planar-diffused technology. The electrical image is composed of M x N discrete information bits with each bit emanating from one of the individual phototransistor sensors. The interconnected mosaic concept was introduced to provide a structure which is both manageable in its number of leads and compatible with conventional viewing systems which accept XY data. Interconnections along the Y direction are provided by internally diffused strips, while interconnections along the X direction are formed by vacuum-deposited metal surface bars. Unique access to any individual element of the M x N mosaic is available through one of the M and one of the N external leads. PHOTOTRANSISTOR DESIGN A phototransistor structure2 was selected for the discrete photon detectors of which the mosaic is com- posed. Basically, the mode of phototransistor operation is such that incident quanta are absorbed in the base area of the element where they generate electron-hole pairs. If the electrons are liberated within a diffusion length of the depletion region around the collector junction, they will diffuse to this depletion region and be swept across the junction where they account for a small component of the photocurrent. Similarly, the holes which are created within a diffusion length of the emitter junction will diffuse to this region where they forward bias the emitter and so induce injection of minority carriers into the base. This accounts for the substantial transistor photocurrent. This mechanism of operation implies several design and fabrication goals for the individual sensor elements: high electrooptical conversion efficiency, sufficient carrier lifetime in the base regions, and a maximum volume in which photons can be absorbed within a diffusion length from the depletion layer about the junction. Moderately high transistor gain is desirable to permit readout at low light levels; however, very high gain has a deleterious effect on mosaic dynamic range. The mosaic must also be characterized by good uniformity of element response as well as by good isolation between elements. The above set of conditions imply that junction depths must be optimized with respect to photon ab-

Jan 1, 1967

By Robert L. Gower, John H. Cash

Interconnections for integrated circuits operating at rnicrowaue frequencies rzust be formed as microwave transmission lines. This paper describes the fabrication of one type of microwave transmission line known as microstrip, which can be fabricated on momlithic integvated circuits by deposition of 0.1- to 2.0-mil-thick metal and dielectric films. A microstrip line consists of a narrow conducting strip separated from a gvound plane by a dielectric material. Thick films of good conducting materials are required for low loss at high frequencies. Vacuum-evaporation methods for depositing aluminum and silver films are described. The narrow conducting strip forming the top conductor is defined by photoresist-etching techniques after the thick rnetal film is deposited. Gold plating with a photoresist-masking technique is also used to forrrz thick metal conductors. The microstrip dielectric layer is formed by deposition of suitable dielectric films 0.1 to 2.0 mils thick. Several deposition techniques were investigated. Electron-beam evaporation of quartz is described. Electrical characteristics of deposited microstrip lines at microwave frequencies are included and the microwave power attenuation as a function of conductor and dielectric thickness is given. It is concluded that the deposition of microstrip transmission lines is a practical way to achieve low-loss interconnections in monolithic integrated circuits. CONNECTIONS between devices in low-frequency and digital circuits are usually made by connecting the devices with a length of conductor such as a metal lead oi- a wire. If this method were applied to microwave integrated circuits, the reactance of the connection due to the series inductance and parasitic capacitance would be very high, in fact too high to permit successful circuit operation. In addition, resonance and antenna effects would occur at high frequencies, especially when the connections approach the wavelength.' Connections which are sections of transmis- sion line will overcome these difficulties. The electromagnetic field is confined to the volume of the transmission line, parasitic effects are not present, and circuit design utilizes familiar transmission-line techniques. TRANSMISSION LINES One type of transmission line geometrically adaptable to integrated circuits is known as micrstri. A microstrip line can be generated from a coaxial line as shown in Fig. l(a). The outer conductor of the coaxial line is distorted into an ellipse (b) and finally separated at the extremities of the ellipse to form the strip transmission line shown in (c). One of the ground planes is then removed, leaving a conducting ground plane and a narrow conducting strip separated by a dielectric. Two configurations of the microstrip line were considered in this investigation, Fig. 2. Type (a) is fabricated from a semiconductor slice with the ground plane and top conductor deposited on each side of the slice. The semiconductor slice serves as the die lec-

Jan 1, 1967

By C. D. Thurmond

Jan 1, 1968

By E. W. Mehal, R. W. Haisty, D. W. Show

The next generation of integrated circuits will probably include circuits constructed in and of GaAs. The existence of both semi-insulating and semiconducting forms of GaAs is the fact which will bring this about. In this paper we discuss the uses and limitations of semi-insulating GaAs for integrated-circuit applications. The two main areas considered are the electrical isolation that can be achieved between components on a semi-insulating substrate and the characteristics of p-n junctions in contact with semi-insulating GclAs. A process basic to attaining integrated circuits in GaAs to fully utilize the insulating properties of the substrate is selective epitaxial deposition. This process involves the deposition of a SiO2 layer onto a The trend in integrated circuits is towards the use of high-resistivity substrates or regions to achieve component isolation. The use of SiO, layers in the oxide isolation methods and the use of sapphire substrates are examples of this idea. GaAs is also a polished surface of a GaAs substrate, etching out selected area of the SiO, film to expose a GaAs surface, and deposition only onto the exposed GaAs surface. By using this process , islands of semiconducting GaAs are deposited onto a semi-insulating GnAs substrate, the islands being electrically isolated from one another by the substrate. The deposition of both p- and n-type semiconducting GaAs can be carried out in this nzanner to form p-n junctions in the island areas. This process can also be used to produce a planav structure by deposition of GctAs through a SiO, mask into holes etched into the GaAs substrate. This Putterned Epitaxial Technology (PET) is described. very promising material for use in future integrated circuits because of the existence of both semi-in-sulating and semiconducting forms. Active devices can be fabricated in the semiconducting material, and these individual components can then be electrically isolated from one another by using semi-insulating GaAs as the substrate. Epitaxial semi-insulating GaAs can also be produced thus making three-dimensional monolithic integrated circuits feasible.' This paper describes the research aimed at developing the methods for producing both two- and three-dimensional integrated circuits in GaAs, and examines some of the properties of semi-insulating GaAs as they relate to these integrated circuits.

Jan 1, 1967