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Jan 1, 1968

By M. Khorouzan, L. Thomas

Designers of semiconductor devices have been strivi,ng to resolve problems associated with Au-A1 alloys in bonded in.tercomzeclions. One approach now being- used is that of waintaining a physical seyav-atioz between the two metals in bond areas. This is accolrzplished by alunzincnz-plating a bonding area on the tips oJ the kovar leads and using alcminurn wires to join the senzicondictor device to the leads. The portion of the kovar lead which is on the externul side of the sealed package is gold-plated to provide an oxide-free surface for soldering or welding. A discoloration condition originally thought to be sinilar to purple plague, occuving in the yluled uluninur bonding area after package sealing, has been investigated to determine its efiects ipm bond integrity. Electron-micro-probe analysis determined that no1 only gold, but lead, zinc, and silicon were also present in the discolored area. A series of samples conlaining' conkrolled umonts of these inzpitrities weve prepared and subjected to a sil.zuluted sealing process. The investigations swcued that, of the contawiinants, only zinc toas detrinenlul to Lhe bond integily. The discoloration condition itself was found not to be detrimental to the bond integrity. DESIGNERS of semiconductor devices have been striving to resolve problems associated with Au-A1 alloys in bonded interconnections. One approach now being used is that of maintaining a physical separation between the two metals in bond areas. This is accomplished by aluminum plating a bonding area on the tips of the kovar leads and using aluminum wires to join the semiconductor device to the kovar leads. The portion of the kovar lead which is on the external side of the sealed package is gold-plated to provide an oxide-free surface for soldering or welding. Contamination as evidenced by discoloration of the aluminum-plated area was observed in a number of integrated circuits undergoing examination for defect characteristics which cause electrical failures.' This paper contains the results of an investigation to determine the nature of this discoloration, its cause, and its effect upon the integrity of the interconnection bond. I) THE NATURE AND EXTENT OF ALUMINUM-BOND CONTAMINATION The initial hypothesis in the investigation was that the discoloration was caused by reaction of the aluminum film with some unknown contaminants during the sealing of the hermetically sealed integrated-circuit flat package. The package is a rectangular ceramic container sealed with glass which surrounds the kovar leads as well as joining the top to the bottom. The seal is made hermetic by heating and cooling the package to devitrify the glass. In the case of the packages under investigation, the hermetic sealing had been accomplished with dry air as internal atmosphere. The apparent effect of contaminations as observed by microscopic examination was the formation of surface oxides having variations in color encompassing the whole spectrum of visible light. The contamination appeared to be related to one of the more notorious examples of these colorations, the so called purple plague.' In addition to purple plague, Fig. 1 shows the tarnish in the luster of the aluminized surface in the bond area which had been observed in many of the integrated circuits. To identify the contaminant in the bond area electron-probe microanalysis techniques were used.3 Fig. 2 shows the result of this analysis. The contaminants identified were gold, aluminum, zinc, lead, silicon, and cobalt. Fig. 2(a) is a back-scatter display of the area under study. The back-scattered electrons provide a general indication of the distribution of elements in the specimen surface. Elements with higher atomic number scatter more electrons back from the surface and are seen as light areas in the picture. The sample current, Fig. 2(b), is the amount of current conducted by the specimen as a result of electron-beam striking it and is an indication of element distribution. The Sample current is the reverse of back-scatter and complements it. Other pictures in Fig. 2 are produced by characteristic X-rays generated by the elements, allowing the isolation of the element of interest. The isolated element appears white and all other elements are dark. In this manner a comparative study provides a correlation between different surface areas and the elements which are in these areas. The area covered by the gold film, Fig. 2(c), shows that the boundary between the gold film and the kovar is not sharp as expected and that some sort of diffusion has taken place. Fig. 2(c) shows that some gold particles have been carried to the bond area and are in the proximity of the bonded wire in spite of the presence of a physical barrier in the form of the un-

Jan 1, 1967

By Hollis L. Caswell

The present status of integrated circuits utilizing. superconductive switching. elements is reviewed with special attention given to fabrication techniques, methods for interconnecting completed circuits, and refrigeration requirements. Cryoelectronics has been largely an "inte- grated-circuit" technology since its conception because the switching speed of superconductive devices is attractive only when these devices are fabricated with thin-film techniques. It is true that cryotron circuits can be constructed from wires of appropriate materials (as indeed was done by Dudley Buck 1 in his early investigations) but these circuits will switch in times characteristic of milliseconds whereas similar circuits fabricated by thin-film methods have potential switching times of nanoseconds. Furthermore, cryo-electronic devices such as the cryotron lend themselves readily to fabrication by thin-film techniques since these components may be made from polycrys-talline thin films and are relatively insensitive to the presence of impurities (as measured by semiconductor standards). Therefore, during the past decade considerable effort has been devoted to developing techniques for batch fabricating circuit arrays containing superconductive switching elements. Technology had developed to the point several years ago that fabrication of cryoelectronic arrays containing up to one hundred devices was rather straightforward. However, larger arrays containing between lo4 and 106 components which are required for commercial development of cryoelectronics still pose very severe yield problems. Thus in a sense cryoelectronics found itself in 1962 at the point semiconductor technology finds itself today; namely, individual devices and small groups of integrated devices could be fabricated with acceptable yield and the outlook for building larger integrated-circuit arrays was bright. Unfortunately, problems associated largely with yield have made fabrication of these larger arrays difficult. Unlike semiconductor technology, cryoelectronics had to solve the problems of large-scale integration before it could become economically attractive. This has proven to be a sizable burden to bear. Since several reviews exist on superconductivity,2 superconductive devices,3 and cryoelectronic technology, no attempt will be made in this paper to summarize these areas. Instead a few specific topics will be dealt with in more detail. First, a brief description is given of selected superconducting switching and storage devices with special attention to several metallurgical techniques which improve the performance of these devices. Second, techniques used to fabricate cryoelectronic devices are described with emphasis on problems affecting yield. Third, techniques for interconnecting a number of cryoelectronic planes are described. And last, refrigeration of cryoelectronic components is discussed briefly since the low operating temperature of superconductive devices is an important consideration in this technology. SUPERCONDUCTING STORAGE AND SWITCHING DEVICES The basic superconductive switching device is the thin-film cryotron. The geometry of this device is attractively simple, since it involves only the intersection of two lines that are electrically insulated from each other. The switching element (gate) and control element (control) of a crossed-film cryotron are arranged as illustrated in Fig. 1. The material for the gate is selected to permit the gate to be switched from the superconducting to the normal (resistive) state by the application of a control current. Tin, which has a critical temperature (T,) of 3.7°K, is commonly used for the gate and the cryotron is operated at a temperature just below T, (for example, 3.5°K). The control material (normally lead, with T, = 7.2°K) is chosen so that the control is never driven normal during circuit operation. To improve cryotron operation, a ground plane, also of lead, is placed under all of the circuitry to act as a diamagnetic shield and improve the current-density uniformity across the width of various thin-film elements. Normally, line widths vary from 0.005 to ^ 0.020 in. and film thicknesses from 300 to 10,000A, although new fabrication techniques make narrower lines feasible. In fabricating cryotrons it is important that the edges of the gate elements be geometrically sharp to avoid undesirable switching characteristics associated with a thinner edge region, Fig. 2. One technique which has been used extensively to form patterns consists of placing a physical mask containing the film pattern between the evaporation source and the substrate and depositing through the mask. Film strips formed in this manner possess a penumbra at the film edges due to shadowing of the evapor-ant under the mask. Several techniques have been proposed for minimizing effects due to this penumbra. One of the more promising metallurgical techniques

Jan 1, 1967

By R. M. Lumley, J. D. Wood

In this investigation, polyethylene terephthalate (Mylar) was coated with various thicknesses of a vapor-deposited silvel- precoat followed by a uapor-deposited zinc using several orders of- magnitude variation in deposition rate of both the silver and zinc. The grain size and resistivity of the zinc film was primarily a function of the silver precoat thickness (in the range of 0.001 to 10 average Agprecoat thickness) and a secondary function of the zinc film thick-ness. The silver and zinc deposition rates were found to have a minor effect on the characteristics of- the zinc film. Electron and X-ray dilffraction results slwwed that all zinc films exhibited a fiber texture mith the (0001) axes essentially perpendiculav to the platze of the film When coating nonmetallic substrates such as paper or plastics with zinc metal vapors, it is found that the zinc will not condense unless extremely high evaporation rates or very low substrate temperatures are used. In 1931, Fraser' reported a procedure whereby zinc could be made to condense on nonmetallic substrates by depositing a very thin precoat of silver. Utilizing Fraser's method, the ermans' developed a commercial process of making "metallized film" capacitors during World War 11. The metallizing process, which was introduced in the United States shortly after the conclusion of World War 11, became one of the first large-scale commercial applications of vapor-deposited metal films and remains one of the larger applications in the electronics industry. The process, as developed by the Germans, consisted of depositing a thin precoat of silver on lacquered, kraft paper followed by a conducting layer of zinc. The resulting silver-zinc film was used as the capacitor The term silver-zinc will be used throughout thiz paper to mean a metal film formed by an extremely thi layer of silver, 10A or less in average thickness, and a zinc film IOOA or more in thickness deposited on the silver film. ---. electrode with the lacquered paper being the dielectric. When polyethylene terephthalate was marketed by E. I. Du Pont Co. in the early 1950's under the trade name Mylar it was substituted for the kraft paper in many capacitor applications. Even though manufacture of metallized paper and metallized Mylar capacitors has been a large commercial process for many years, little information has been published about the deposition parameters. Correlating the work of others to the various effects to be expected of deposition parameters on silver-zinc films deposited on Mylar, it is expected that the

Jan 1, 1967

By William K. Antle

The successful application of ther mo compression lead bonding to semicondtctor or thin-film electronic devices depends on the establishment of the associated parameters. The quality of a thermocompression bond is primarily related to the process temperature and bonding force. A technique using the coelyicient of friction is presented that both reduces the time necessary for determining optimum parameter values and increases the accuracy of the results. Modern theories of the friction process are used to develop mathernatical expressions for shear and tensile bond strengths in terms of friction measurements. A further application of the pararneter-deterlnination technique concerns the measurement of surface contamination that may affect thermocompression bonding. In spite of the extensive use of thermocompression bonding, adequate methods for determining the bonding parameters have not been utilized. The quality of the weld depends on the temperature, force, and time used. There is a definite value or range of values for each parameter which assures an optimum weld. The process now generally used to obtain these values is to make several weld samples at each parametric setting, determine the mean pull strength, and relate the maximum consistent strength to optimum weld conditions. This could involve a very large number of test samples if a thorough search of each parameter were made. Experience and prior knowledge can reduce this number somewhat by limiting the investigation to a range known to contain the correct value, but the time and effort involved are still objectionable. The problems associated with thermocompression bonding of interconnecting leads to semiconductor or thin-film devices can be alleviated by the application of a new technique for establishing the process parameters. Obtaining the correct temperature, force, and duration to assure an optimum bond is accomplished by a simple measurement of the coefficient of friction. This approach increases the accuracy of parameter determination and greatly reduces the time necessary to complete the process. The approach made can be better understood by analyzing the principles of adhesion and friction on which thermocompression bonding depends. When two flat polished surfaces are placed together, the area of actual contact is much less than the apparent area determined by the over-all dimensions of the surface. This is because the microscopic surface is covered with projections which prevent uniform contact. Careful measurements of the electrical resistance across the contacting surfaces indicate the actual area may only be 1100,000 of the apparent area.' Because the actual contact area is small, extremely high pressure results from moderate force. This will produce deformation and plastic flow at contact points of the microscopic projections. The process will terminate in the creation of a large number of minute welds formed at extreme pressure and cold-worked to strong, hard bonds. Load removal will generally result in fracture of most of these microbonds because of the residual elastic stresses, unless the materials are soft. Friction between metals is due to the formation and

Jan 1, 1967

By Bernard G. Carbajal

The dielectric properties and thermal stability of glow-discharge polytnerized films of styrene, chloro-benzene, and other organics and photoresist filrns are presented. Variations in the glow-discharge polymerization procedure are related to thermal stability. Thermal treatwzents to improve the dielectric properties of both positive (A2 340) and negative (KMER) photoresists are given. THIS study of the dielectric properties of thin organic polymer films is part of a program to investigate the electronic applications of organic materials. Thin organic polymer films have been produced in an ac glow discharge,13 with a low-energy electron-beam process,4 and in an rf dicharge. A process has been developed during the course of this program for forming thin organic polymer films in a dc glow discharge. These glow-discharge polymerized (GDP) films exhibit some useful dielectric and insulative properties. Variations in the properties of the GDP films can be induced by changes in the source material (monomer) andor in the conditions of the glow discharge. Thin organic polymer films can also be produced from typical positive and negative photoresists. Some variations in the properties of the photoresist films can be induced by suitable post-application treatments such as thermal crosslinking. The properties of interest in this study are dielectric constant, dielectric strength, resistivity, and thermal stability. POLYMER FILM PREPARATION I) GDP Films. The GDP films were prepared in a dc glow discharge in an atmosphere of organic monomer vapor. The details of the glow-discharge procedure have been presented previously.6 Briefly, under the influence of a dc glow discharge organic vapors can be polymerized in the vapor phase and the resultant polymer (GDP film) deposits on and in the vicinity of the cathode. Substrates placed behind a screen cathode can be uniformly coated over all exposed areas. Pattern definition can be achieved using normal mask stencil techniques. Table I presents the pertinent parameters in the preparation of GDP styrene. Conditions of Forrrzation of GDP Styrene. The rate of deposition for GDP films was monitored using a current-time integrator. The thickness of the deposited film for a given set of experimental conditions was a function of the current-time integral. The fifth row in Table I is a compilation of the deposition rate of GDP styrene films. Other organic monomers behave in a similar fashion. With the exception of the highly halogenated saturated hydrocarbons, all organics subjected to the conditions of the glow discharge form GDP films. 11) Photoresist Films. Photoresists are normally recognized to exist in two forms, a low molecular weight, soluble polymer form (A) and a high molecular weight, crosslinked insoluble form (B). Typical negative photoresists are applied in the low molecular weight form A and converted to the high molecular weight form B by the action of light. (Positive photoresists are applied in form B and converted to form A by the action of light.) Eastman Kodak Metal Etch Resist (KMER) has been chosen as a typical negative photoresist. Polymer film samples were prepared in the same configuration used for GDP films. The KMER was applied in the usual fashion using a 120°C drying step (infrared-lamp heating) and a 180°C post-bake. Care must be taken to completely remove the solvent in the drying step and to properly develop and postbake to exposed photoresist. If the photoresist film is not properly dried and postbaked, severe blistering and peeling will occur during subsequent elevated-temperature exposure. Thickness can be controlled by varying the viscosity of the form A photoresist and the spin rate at application. AZ 340 was chosen as a typical positive photore-

Jan 1, 1967

By F. V. Shallcross

Physical properties of thin films of CdS and CdSe formed by vacuum deposition onto glass sibstrates have been studied as a function of deposition and processing conditions. The crystallinity and surface features of CdS films were examined using electron microscopy and electron and X-ray diffraction techniques. The films were poly crystalline; the preferred orientation and crystallite size increased with film thickness, substrate temperature, and deposition time. The CdS films consisted primarily of hexagonal-phase material, in contrast to similarly prepared CdSe films which have previously been observed to contain mixtures of cubic and hexagonal phases. As-deposited CdS films showed no major dependence of Hall mobility on crystallite size or degree of preferred orientation. Hall mobility and carrier concentration in CdS and CdSe .films were measured at various temperatures; both parameters increased with temperature and yielded activation energies which depended on fabrication conditions. Surface-desorption phenomena and overcoating of the semiconductor with SiO affected the observed electrical properties significantly. THIN films of cadmium sulfide1,2 and cadmium sele-nide3,4 have been employed by various workers as semiconductors in the insulated-gate thin-film field-effect transistor, known as the TFT. These devices are most commonly made by vacuum deposition of all materials onto an amorphous substrate such as glass. A knowledge of the microstructure and electrical properties of semiconductor layers used in the thin-film transistor is essential in order to form a realistic model for the device and to improve its performance, reproducibility, and reliability. This paper will describe studies of the physical properties of vacuum-deposited CdS and CdSe films prepared under various conditions. Structural characteristics examined in- cluded phases present, crystallite size, nature of preferred orientation of crystallites, surface roughness, and structural homogeneity throughout the film thickness. Electrical properties measured were Hall mobility and conductivity and their dependence on temperature and ambient. Thin-film properties are affected by many fabrication parameters including purity and physical form of evaporant, deposition rate, film thickness, design and temperature of the evaporation crucible, geometry of the deposition chamber, nature of the residual atmosphere, composition and temperature of the substrate, and details of postdeposition processing. PREPARATION OF FILMS In this work the semiconductor films were deposited in a conventional oil-diffusion-pumped system with pressures in the 10-8 torr range. The CdS evaporant was obtained from the Eagle-Picher Co. as a high-purity coarse-grained crystalline powder; the CdSe was a high-purity sintered powder supplied by the Harshaw Chemical Co. The evaporation crucible was a resistance-heated molybdenum-wire basket coated with aluminum oxide and filled with a quartz wool plug at the top. The source to substrate distance was usually 10 cm. This region was enclosed by a Pyrex inner cylinder. The substrate was heated with an overlying Pyrex plate coated with tin oxide. The substrate temperature was controlled using a thermocouple attached to the lower side of the heater. This thermocouple was calibrated against another thermocouple attached to a dummy substrate and by observation of melting points of various metal films deposited in the system. The substrates were polished borosilicate glass plates and conventional glass microscope slides. Substrate preparation included cleaning with an ultrasonically agitated detergent bath followed by isopropanol-vapor de-greasing. Film thickness was measured interferomet-rically during and after deposition. STRUCTURE OF CdS FILMS Structural studies were performed on CdS films using electron diffraction, electron microscopy, and

Jan 1, 1967

By T. G. R. Rawlins, L. E. Brosselard

Direct platinum carbon replicas have been used to study substrates prior to growth and after initial nu-cleation of the layer. Replicas have been directly stripped and correlations have been made with other replica techniques. Mechanically polished substrates are very flat with occasional areas of "dirt", which is apparently silicon. When such substrates are etched in hydrochloric acid gas, scratches and hexagonal defects (thought to be polishing compound) are revealed, together with areas of apparent redeposition. Chemically polished substrates are much less flat although much more homogeneous in appearance. Heat treat)nents have no effect. Nuclei deposited on these surfaces, using a normal silicon tetrachloride system, have been examined. Nuclei on mechanically polished subsrates occur in random areas only, whereas on chemically polished surfaces they are more uniformly distributed. THE interest in the study of thin films and now their rapidly expanding use in many fields has increased over a period of years. Much of this current interest, particularly in the field of single-crystal or epitaxial thin films, has derived its stimulus not only from possibilities for application but also from fundamental electron-microscope studies which have indicated the manner of growth of such layers from the initial nuclei.1-5 Previous work involving study of growth processes may be divided into three categories. First, vacuum deposition, primarily of metals, on a variety of substrates has been studied by electron microscopy and electron-diffraction techniques. These have shown the three-dimensional aspect of nucleation and the remarkable liquidlike behavior of the growing nuclei which coalesce to form a complete layer. More recently this work has been expanded in two ways: by growth inside the electron microscope this has obvious advantages for kinetic studies; and by growth in ultrahigh vacuum—much of this work has been done on semiconductors.8-11 It is of interest to note that metals, specifically gold deposited on rock salt, will form only polycrystalline layers in ultrahigh vacuum unless the substrate surface is contaminated.12 In general the mode of growth for vacuum-deposited semiconductor films is the same as that for metal films. The second method of growth that has been studied is that of electrodeposition.13,14 The little that has been published suggests that the mode of growth is similar to the vacuum case, except that irregularities may perturb the electric field and disturb the growth process. The third and last primary method of growing epitaxial layers is by use of chemical methods. These techniques have generated much interest and much has been published on them. Considerable electron-microscope work has been done on the defects in the layers; however comparatively little work has been undertaken on the initial nucleation and early stages of growth. Confining ourselves now exclusively to the case of silicon, Charig et a1.15 have considered the growth of silicon on silicon substrates by hydrogen reduction of trichlorosilane, and studied the films by means of replica and transmission techniques. Subsequently they have studied the same system for growth on quartz,16 and with the addition of pyrolysis of silane on quartz and alumina.17 Also Manasevit el al. have studied deposits using silane and silicon tetrachloride on sapphire.18-14 Finally, in this volume studies of deposition on beryllia and sapphire are reported. Although Revesz and Evans20 have examined complete layers, grown by means of the widely used silicon tetrachloride reaction, no detailed examination similar to that published by Charig and Joyce21 for the trichlorosilane system has been given. Therefore this investigation has examined substrate surfaces prior to growth and then nucleation on these surfaces for the silicon tetrachloride system. EXPERIMENTAL In this work the surfaces have been studied by means of standard replica techniques. Because of the very real problems associated with artifacts introduced,22 different replicas and different cleaning

Jan 1, 1967

By J. P. Pritchard, J. T. Pierce, O. G. Slay

This paper discusses the results of a technology-evaluation program to ascertain the feasibility of a piotornask-photoresist technology developed for fabrication of multiple-layer thin-film superconductive circuitry. The uehicle selected for this evaluation was a 120-bil associative data processor requiring a set of nine photomasks to define a similar number of patterned material layers of lead, tin, and polymer insulation. A total circuit area of 4 sq in. involved 2500 actitle and 12,000 passive crossings. Several short-free, electrically continuous specimens were satisfactorily completed under this program. Problems encountered in the preparation and use of the requi-ed set of Photomasks are discussed, as also are the problets of providing suitable external connections. A major retarding factor in the development of the superconducting thin-film cryotron technology for many years was the absence of batch fabrication means yielding necessary device density and count per substrate for practical applications. Early workers in the field desired only limited numbers of devices to permit careful study of discrete devices and representative circuitry integrating logic and memory capabilities. For these purposes mask stencils could be formed to selectively control the placement of materials, sequentially vapor-deposited in vacuum, to form the multilayer structure. In general a distinct pattern was required for each material layer; therefore, mechanical provisions were required to change not only the material source, but the patterning mask as well, before each deposition. All deposition steps were preferably performed in a single evacuation of the deposition chamber. Thus the means for storing, transporting, and registering masks and sources with respect to the substrate existed and were operated within the vacuum environment. In the authors' experience, the approach was and remains serviceable for preliminary device study, but was not extensible to an economical manufacturing method by virtue of the difficulties inherent in mask stencil preparation and use, and the capital investment implicit in the mechanization requirements. Since the commercial attraction of the cryotron technology stems principally from its potential for economical batch fabrication, the authors' program has placed major emphasis on fabrication methods. A highly useful method has evolved through adaptation

Jan 1, 1967

By William F. List, Marvin A. Schuster

Monolithic electrooptical mosaics of 2500 photo-transistor elements with internal row and surface column interconnections have been fabricated by epitaxial-planar diffsion techniques. Unique access to any elemed of the mosaic is provided through one of the fifty X and one of the fifty Y external leads. The sensor mosaic can be used for imaging applications and has a 1:1 aspect ratio, a resolution of 100 lines per in., a dynamic range in excess of lo3, a sensitivity of 0.5 per pw, element response within a 2:l range over 75 pct of the mosaic, and a minimum detectable signal of the order of 10-' w. Design considerations which ilnpose particclar fabrication yequirements are disctussed along with some of the problems peculiar to the epitaxial and planar-dijfision techniqes by which this device is fabricated. The solid-state silicon monolith has an imaging area of 0.5 by 0.5 in. and an element center -to- center spacing of 0.010 in. J monolithic solid-state electrooptical device has been developed as the photon-sensing mosaic for use in an image-converter system.' This system is the solid-state equivalent of the vidicon and can image radiation in the visible and near-infrared regions of the spectrum. The electrooptical image converter has the desirable size, weight, reliability, and low-power characteristics inherent in solid-state devices. It is read out by direct-wire means rather than by beam-scan techniques. The packaged unit is shown in Fig. 1. A selection of material for the sensor was based on considerations of both reliable fabrication techniques and material spectral response. Silicon was selected both for its response from the lower end of :he visible to the long-wavelength cut-off above 11,000A and for its well-developed epitaxial planar-diffused technology. The electrical image is composed of M x N discrete information bits with each bit emanating from one of the individual phototransistor sensors. The interconnected mosaic concept was introduced to provide a structure which is both manageable in its number of leads and compatible with conventional viewing systems which accept XY data. Interconnections along the Y direction are provided by internally diffused strips, while interconnections along the X direction are formed by vacuum-deposited metal surface bars. Unique access to any individual element of the M x N mosaic is available through one of the M and one of the N external leads. PHOTOTRANSISTOR DESIGN A phototransistor structure2 was selected for the discrete photon detectors of which the mosaic is com- posed. Basically, the mode of phototransistor operation is such that incident quanta are absorbed in the base area of the element where they generate electron-hole pairs. If the electrons are liberated within a diffusion length of the depletion region around the collector junction, they will diffuse to this depletion region and be swept across the junction where they account for a small component of the photocurrent. Similarly, the holes which are created within a diffusion length of the emitter junction will diffuse to this region where they forward bias the emitter and so induce injection of minority carriers into the base. This accounts for the substantial transistor photocurrent. This mechanism of operation implies several design and fabrication goals for the individual sensor elements: high electrooptical conversion efficiency, sufficient carrier lifetime in the base regions, and a maximum volume in which photons can be absorbed within a diffusion length from the depletion layer about the junction. Moderately high transistor gain is desirable to permit readout at low light levels; however, very high gain has a deleterious effect on mosaic dynamic range. The mosaic must also be characterized by good uniformity of element response as well as by good isolation between elements. The above set of conditions imply that junction depths must be optimized with respect to photon ab-

Jan 1, 1967

By Robert L. Gower, John H. Cash

Interconnections for integrated circuits operating at rnicrowaue frequencies rzust be formed as microwave transmission lines. This paper describes the fabrication of one type of microwave transmission line known as microstrip, which can be fabricated on momlithic integvated circuits by deposition of 0.1- to 2.0-mil-thick metal and dielectric films. A microstrip line consists of a narrow conducting strip separated from a gvound plane by a dielectric material. Thick films of good conducting materials are required for low loss at high frequencies. Vacuum-evaporation methods for depositing aluminum and silver films are described. The narrow conducting strip forming the top conductor is defined by photoresist-etching techniques after the thick rnetal film is deposited. Gold plating with a photoresist-masking technique is also used to forrrz thick metal conductors. The microstrip dielectric layer is formed by deposition of suitable dielectric films 0.1 to 2.0 mils thick. Several deposition techniques were investigated. Electron-beam evaporation of quartz is described. Electrical characteristics of deposited microstrip lines at microwave frequencies are included and the microwave power attenuation as a function of conductor and dielectric thickness is given. It is concluded that the deposition of microstrip transmission lines is a practical way to achieve low-loss interconnections in monolithic integrated circuits. CONNECTIONS between devices in low-frequency and digital circuits are usually made by connecting the devices with a length of conductor such as a metal lead oi- a wire. If this method were applied to microwave integrated circuits, the reactance of the connection due to the series inductance and parasitic capacitance would be very high, in fact too high to permit successful circuit operation. In addition, resonance and antenna effects would occur at high frequencies, especially when the connections approach the wavelength.' Connections which are sections of transmis- sion line will overcome these difficulties. The electromagnetic field is confined to the volume of the transmission line, parasitic effects are not present, and circuit design utilizes familiar transmission-line techniques. TRANSMISSION LINES One type of transmission line geometrically adaptable to integrated circuits is known as micrstri. A microstrip line can be generated from a coaxial line as shown in Fig. l(a). The outer conductor of the coaxial line is distorted into an ellipse (b) and finally separated at the extremities of the ellipse to form the strip transmission line shown in (c). One of the ground planes is then removed, leaving a conducting ground plane and a narrow conducting strip separated by a dielectric. Two configurations of the microstrip line were considered in this investigation, Fig. 2. Type (a) is fabricated from a semiconductor slice with the ground plane and top conductor deposited on each side of the slice. The semiconductor slice serves as the die lec-

Jan 1, 1967

By C. D. Thurmond

Jan 1, 1968

By E. W. Mehal, R. W. Haisty, D. W. Show

The next generation of integrated circuits will probably include circuits constructed in and of GaAs. The existence of both semi-insulating and semiconducting forms of GaAs is the fact which will bring this about. In this paper we discuss the uses and limitations of semi-insulating GaAs for integrated-circuit applications. The two main areas considered are the electrical isolation that can be achieved between components on a semi-insulating substrate and the characteristics of p-n junctions in contact with semi-insulating GclAs. A process basic to attaining integrated circuits in GaAs to fully utilize the insulating properties of the substrate is selective epitaxial deposition. This process involves the deposition of a SiO2 layer onto a The trend in integrated circuits is towards the use of high-resistivity substrates or regions to achieve component isolation. The use of SiO, layers in the oxide isolation methods and the use of sapphire substrates are examples of this idea. GaAs is also a polished surface of a GaAs substrate, etching out selected area of the SiO, film to expose a GaAs surface, and deposition only onto the exposed GaAs surface. By using this process , islands of semiconducting GaAs are deposited onto a semi-insulating GnAs substrate, the islands being electrically isolated from one another by the substrate. The deposition of both p- and n-type semiconducting GaAs can be carried out in this nzanner to form p-n junctions in the island areas. This process can also be used to produce a planav structure by deposition of GctAs through a SiO, mask into holes etched into the GaAs substrate. This Putterned Epitaxial Technology (PET) is described. very promising material for use in future integrated circuits because of the existence of both semi-in-sulating and semiconducting forms. Active devices can be fabricated in the semiconducting material, and these individual components can then be electrically isolated from one another by using semi-insulating GaAs as the substrate. Epitaxial semi-insulating GaAs can also be produced thus making three-dimensional monolithic integrated circuits feasible.' This paper describes the research aimed at developing the methods for producing both two- and three-dimensional integrated circuits in GaAs, and examines some of the properties of semi-insulating GaAs as they relate to these integrated circuits.

Jan 1, 1967

By D. H. Forbes, I. B. Cadoff, H. M. Manasevit

Single-crystal silicon films have been obtained on several natural crystal faces of BeO using the thermal decomposition of silane and the hydrogen reduction of silicon tetrachloride. From an analysis of X-ray diffraction data it was determined that the following film-substrate orientation relationships exist: (111) Si 11(0001) BeO, (111) Si 11(1011) BeO, (100) Si 11f1010) BeO. and (110) Si 11(1010) BeO. An analysis of the crystallographic relationships between the film and substrate indicates that a match occurs between the silicon atoms in the film and the berylliuni ion sites in the substrate. This correspondence is in agreement with previous work on the deposition of silicon on sapphire.1-3 silicon on spinel: and tungsten on sapphire. The high resistivity, thermal conductivity, and radiation resistance of beryllium oxide make it an important substrate material for the deposition of thin films of silicon or other semiconductors. The importance of semiconductor-insulator composites to the field of integrated microelectronics has been well-documented in the case of silicon on sapphire.'-' The successful growth of large-area single-crystal silicon on an insulator, sapphire, was first reported in 1963.1,2 Since that time studies have been made of the crystallographic relationships between the deposited film and the sapphire substrate. On the basis of the observed relationships, a model has been proposed relative to the crystallographic requirements for epitaxy between the semiconductor film and the metal oxide substrate.3 It is proposed in this model that epitaxy is the result of a match between atoms of the deposited film and the metal ion sites of the substrate plane. This match is not limited to a 1 to 1 correspondence between sites in the two lattices. Sub- sequent studies of the deposition of silicon on spinel4 and tungsten on sapphire5 have yielded data which support this model. On the basis of this previous work it was felt that silicon on BeO should also fit this model. In the present study, the choice of substrate orientation was limited to the natural faces of synthetic BeO crystals. Of the faces available, the (0001) plane seemed the most favorable for epitaxial growth. EXPERIMENTAL PROCEDURE Silicon films were deposited from silane and silicon tetrachloride in the apparatus shown in Fig. 1. The hydrogen ambient gas was purified by passage either through a DEOXO unit, molecular sieves, and a liquid nitrogen cold trap, or through a heated Pd-Ag thimble. The gas was then mixed with the silicon source materiai and passed over the substrate which lies on a spacer above an inductively heated silicon pedestal. The following deposition conditions were used: a hydrogen flow rate of 3 liters per min with silane and silicon tetrachloride concentrations of 0.2 mole pct and a pedestal temperature of 1175" * 5°C as observed with an optical pyrometer assuming an emissivity of 1.0. Deposition was preceded by a 15- to 30-min hydrogen-etch period conducted at a temperature of 1275°C (obs). Adherent silicon films from 2 to 10 u were grown on the various BeO faces. The substrates were synthetically grown beryllium oxide single crystals ranging from 5 to 10 mm in

Jan 1, 1967

Jan 1, 1967

Jan 1, 1968

By P. K. Weimer

Coinpletely integrated thin-film circuits inco?,porating more than 1000 active and passive elements have been fabricated reproducibly in the laboratory by evaporation of- all components. A 180-stage modified shift register comprising 540 CdSe TFT's, 360 resistovs, and 180 capacitors was deposited upon a glass substrate during one pump-down of the vacuum systeitl. Experimental units have been operated for more than 5000 hr at temperatures uP to 85°C without failure of any slages. The present pupper reviews the charvactevistics of evaporated thin-film transistors (TFT's) and discusses their application to integrnted circuils. INTEGRATED circuits most widely used today are based upon silicon technology, with the circuits formed on the surface of a block of single-crystal silicon1 or on a block of sapphire 2,3 upon which a thin layer of silicon has been deposited. Transistor patterns and interconnections are defined by photographic procedures using photoresist masking. Large groups of transistors are produced in batches which undergo many processing steps, some of which are carried out at elevated temperatures. Passive elements are formed by treatment of the semiconductor surface or are deposited by evaporation alongside the active elements. The size and complexity of the circuits are limited by defects in the devices and by the size of the available single-crystal chips. Capacitative coupling to the semiconducting substrate may also limit useful size and frequency response of the circuits. An alternative approach to integrated circuits is based upon the deposition by evaporation of all circuit components upon a noncrystalline, insulating substrate such as glass.4 Thin-film field-effect transistors,1'6 known as TFT's, can be deposited in large arrays on glass or plastic substrates at the same time the associated passive elements are being deposited. Although still in the research stage the all-evaporated approach is expected to offer certain advantages for many applications. In particular, the use of thin films upon a noncrystalline substrate offers the prospect of producing complex, large-area circuits not now feasible with single-crystal silicon. Important applications of this type include memory arrays for computers and imaging devices for television. The ease with which the evaporated TFT's can be deposited may permit continuous, automated production methods not possible with high-temperature batch processing. Recent advances7'8 in the fabrication of thin-film transistors have led to greatly improved reproduci-bility and life of the TFT's. Experimental circuits having over 1000 active and passive elements deposited upon a common glass substrate are currently being produced in the laboratory. The present paper reviews recent progress in the development of the TFT and in its application to integrated circuits. I) DESCRIPTION OF THE THIN-FILM FIELD-EFFECT TRANSISTOR The TFT is a field-effect transistor of the type having the control gate separated from the semiconductor by a thin insulating spacer. Although its operation resembles that of the silicon MOS transistorg its construction is based entirely on thin-film techniques. Fig. 1 shows a cross-sectional view of an evaporated TFT deposited upon a glass substrate compared with a silicon MOS transistor deposited upon single-crystal sapphire.3 The semiconductor in the TFT is a poly crystal line layer, of a material which can be readily evaporated, such as cadmium sulfide, cadmium selenide,l0 or tellurium." Silicon monoxide layers have usually served as the gate insulator, but other oxides, sulfides, and fluorides may be used. Film thicknesses range from a few hundred to a few thousand angstroms. The source, drain, and gate electrodes in the TFT are of metal. Qpical source-drain gap dimensions are 0.0003 x 0.030 in., with a gate strip whose width slightly overlaps the source and drain. The source and drain electrodes should make low impedance contacts to the semiconductor. With cadmium sulfide films, gold is a satisfactory material for underlying electrodes, while aluminum is preferable for overlying electrodes.12 Considerable variation in design of the TFT is permissible, with the electrodes being

Jan 1, 1967

By P. J. Burkhardt, L. V. Gregor

The oxidation kinetics of single-crystal silicon has been investigated using extremely dry oxygen as the oxidant. Two techniques were used. The first involved a flow system with which incremental thickness measurements were made. This sytem provided an oxygen ambient at atmospheric pressure which had a moisture content of less than 0.1 ppm of water. The second technique involved measuring the change in volume of oxygen with time in a closed system. A temperature range of 900O to 1200 "C and a pressure range of 20 to 760 Tory were covered. Both techniques showed that a simple parabolic rate law holds only at the higher temperatures. At lower temperatures, the data up to 5000Å can be fitted well to a linear-parabolic equation. The two constants in this rate equation are examined in terms of a physical model. The parabolic portion of the low-temperature oxidatLon fits along the high-temperature curve of an Arrhenius plot. The parabolic rate constant for the flow-system technique can be expressed by k = 2 x 10-9 exp (L 31 kcalRT) sq cm per sec. The manostatic technique gave k = 1 x 10-exp (- 23 kcalRT) sq cm per sec. By extending the thickness range to over 104. a rate law of X = At seems to fit all of the data better than the linear-Pavabolic law. Here the exponent n increases from 0.518 at 1150 V to 0.637 at 900°C. PASSIVATION of silicon planar devices through thermal oxidation is of such great importance that considerable effort has been devoted to the study of the process.17 Much of this work involves hydrothermal oxidation, in which H2O is the oxidant: whereby H2 is produced. It has been proposed that the reaction proceeds by the formation of Si-OH groups and hydroxyl diffusion through the film to react with the silicon surface. Thus, the silicon oxide layer probably contains residual hydrogen in some form after oxidation in H2O and it has already been established that hydrogen has a marked effect on the electronic properties of oxide-passivated silicon surfaces. Silicon is oxidized by oxygen at elevated temperatures; but the rate of oxide formation is considerably lower than that for 0." By using dry O2 as the sole oxidant, the presence of residual hydrogen is presumably avoided. At present, the mechanism of thermal oxidation by dry O2 is a matter for conjecture, and the presence of small amounts of H2O was reported to have a marked effect on the rate of oxide formation10 (perhaps on the electronic properties of the surface, as well). Hence, this study of the kinetics of silicon oxide growth in 0, was undertaken: 1) to determine the oxidation rate at atmospheric pressure in a system designed to exclude rigorously all traces of H2O in the ambient 0,; 2) to obtain oxidation-rate data in situ in dry O2 by means of a continuous monitoring of the amount of 0, consumed during oxide growth. These objectives are complementary—the first assesses what effects (if any) are obtained by excluding H2O from the reaction, and the second expands this information while at the same time avoiding the uncertainty inherent in relying upon incremental measurements of oxide growth to furnish kinetic data. EXPERIMENTAL PROCEDURE The conventional silica open tube in a resistance-heated oxidation furnace is subject to sources of trace H2O, even after the input O2 is thoroughly dried and the outlet gas stream is passed through a trap to prevent

Jan 1, 1967

By Richard I. Petritz

A brief review of today's processing of integvated circuits is given. The major trends in the development of advanced integvated electronics are identified as 1) the broadening of the integvated circuit concept to a large class of circuit function, 2) the processing of more complex circuits within relatively small chips of silicon, and 3) the processing of very large electronic functions on complete slices of silicon. This latter trend, called array technology, is then developed in detail. Emphasis is given to defining the key tech-nological problems. Current progress being made is illustrated. THIS paper will endeavor to identify the major trends in advanced integrated electronics technology. One of these, array technology, will be developed in some detail. The array technology discussion will identify the key problem areas. Since it is the scope of the entire meeting' to present specific progress in the science and technology of integrated electronics, we shall indicate general directions being explored rather than discuss comprehensively solutions to the problems. In order to set the stage for the discussion of future trends in integrated-electronics technology, let us briefly compare the processes by which circuits are fabricated through discrete-device technology with that of integrated circuits technology. The reader is referred to the December 1964 issue of Proceedings of IEEE2 for a comprehensive review of integrated electronics. The article3 by Jay Lathrop is an excellent discussion of integrated-circuits technology. A discussion of the history of semiconductor technology is contained in Ref. 4. A) Current Status of Integrated Electronics. Fig. 1 (top) shows the process by which circuits are constructed from discrete devices. Key points are: 1) Slices containing large numbers of transistors or diodes are processed separately. 2) The slices are scribed into small chips (on the order of 15 mils on a side is about as small as can be conveniently handled) each chip containing one transistor. 3) Each device is specified separately—circuit -function specs are derived largely from device specs. 4) Circuits are formed by connecting together the discrete devices. 5) The number of circuit connections required is approximately equal to the number of devices. 6) There are potentially many more discrete devices per inch2 of semiconductor—only our lack of ability to handle them in discrete form prevents us from going to several orders of magnitude higher density iin Fig. 1, 400,000 transistors are discussed at 1.5 mils on a side). The bottom part of Fig. 1 illustrates the integrated circuit process. Key points are: 1) On the same slice of silicon, transistors, diodes, and resistors are processed grouped to do a complete circuit function. 2) While still in slice form, the components are interconnected into circuit functions by an evaporation process, eliminating the need for separate interconnection steps later. Dramatic improvements in cost and reliability are realized. With a simple flash of metalization thousands of interconnections are reliably made. 3) The slices are scribed into chips which contain complete circuit functions. 4) The circuit functions are specified-not each component in the circuit. This important point was missed by some of the early opponents to integrated circuitry. They argued that, with device yields at x pct, integrated circuit yields would be pct, where n is the required number of devices to make a circuit. This argument leads to extremely low yields for integrated circuits. The fallacy of the argument is that in integrated circuits each device is not specified separately. Furthermore, since a device is forever integrated into a specific circuit function, it need meet only the requirements for that particular function. Discrete devices, on the other hand, are tightly specified so that they can be applied to a variety of circuit functions. 5) Extremely high packing densities are achievable because one need only make the basic devices as large as the circuit demands. Their size is not dictated by handling requirements. A current example

Jan 1, 1967

By A. D. McMaster, M. L. Gimpl, N. Fuschillo

Low-power, high-speed, radiation-resistant, monolithic thin-film integrated circuits require thin-film resistors of high sheet resistance which are compatible with the processing requirements for monolithic silicon devices. For this purpose the structure and electrical resistance as a function of temperature were investigated for Nichrome-silicon monoxide cermet films on passivated single-crystal silicon substrates. A suitable material was found to be a mixture of 50 vol pct Nichrome-50 vol pct silicon monoxide. This mixture, when evaporated onto 300°C substrates. showed a low temperature coefficient up to 400°C, at both 270 and 1100 ohms per square. Resistors deposited on room-temperature, 300°, and 500°C substrates were heat-treated at 600°C in air for short periods of H- seed, low-power, radiation-re sis tant, monolithic thin-film integrated circuits'-3 require thin-film resistors of high sheet resistance and low temperature coefficients of resistance which are compatible with the processing requirements for monolithic silicon active devices. The present investigation is directed towards the replacement of the Nichrome in the sandwich-type SO2-Nichrome-SiO resistors, currently used for DTL monolithic thin-film integrated circuits, with codeposited Nichrome-SiO cermet resistors. These Nichrome-SiO resistors are provided with an overcoat of SiO and are deposited onto thermally oxidized silicon wafers used in monolithic mi-crocircuit technology. The cermet resistors are shown to provide a lower temperature coefficient of time totaling up to 45 min. Electron nzicrogvaphs and diffraction patterns were taken of the as - deposited and heat-treated films. These results were then compared with electrical-resistance measurements for each condition. The room-temperature and 300°C substrate films showed a large decrease in resistance. The 500°C substrate film remained stable throughout the entire cycle. Electron-microscopy results show that the increased stability after heating to 600°C is largely due to crystallization of the films which begins in the vicinity of 400°C. The slight oxidation of the films when heated in air had a negligible effect on the resistance. The resistance of the film was a function of the substructure. resistance and a more versatile compatibility with silicon monolithic processing. Previous work3, on chromium-SiO coevaporated cermet resistors on glass and ceramic substrates without overcoats of SiO has been reported. For the present application, the thin films should possess the following ideal requirements: a) a temperature coefficient of resistance as near zero as possible up to 300°C; b) have a sheet resistance higher than 200 ohms per sq to conserve space on the chip; c) be easy to evaporate; d) be oxidiation- and radiation-resistant; e) show long-time stability at 100°C; } be stable in N2 atmospheres up to 600°C for short periods of time (5 to 45 min). Requirements a to e are well-known. The last requirement was optional and was due to a mask elimi-

Jan 1, 1967